Recently there has been concerted effort among researchers and engineers to protect integrated chip circuitry from the troubling effect of natural background radiation. Natural background radiation, in the form of energetic alpha particles and neutrons, has become an increasingly difficult problem to solve as transistor size shrinks with each new generation of chips. High-energy particle irradiation can corrupt data stored in memory chips, producing what engineers refer to as "soft errors". As the semiconductor industry progresses toward line widths as fine as 0.18 microns, soft errors in data pose a major challenge.
A number of different approaches have been tried to reduce soft error rates in semiconductor devices. By way of example, U.S. Pat. No. 5,691,089 discloses a transistor device in which a doped layer of a radiation sensitive material is formed a substrate. The radiation sensitive material may be polyamide or a similar organic dielectric. The inventors attribute improved alpha particle immunity to the complete isolation of the SRAM array by the organic dielectric layer.
A semiconductor memory array that reduces the probability of soft errors ascribable to alpha particles is also described in U.S. Pat. Nos. 5,365,478 and 5,732,037. These patents disclose a circuit solution applied to a dynamic random-access memory (DRAM). Another example is provided in U.S. Pat. No. 5,065,048, which teaches specialized precharging operations that enlarge the soft error margin against alpha particle strikes in CMOS and BiCMOS logic circuits. Yet another approach to the problem of soft errors in semiconductor memory devices is described in U.S. Pat. No. 5,301,146.
In order to deal effectively with the problem of soft errors, it is necessary to have a reliable method to predict soft error rates (SER) for various circuits at the physical design level. One commonly used method is to examine the total quantity of charge stored at a given circuit node. This previous method is typically based on experimental data from static random-access memories (SRAM), such as that shown in FIG. 1.
FIG. 1 illustrates a simple memory cell 10 comprising field-effect devices 11-14 arranged as cross-coupled inverters. In its basic operation, memory cell 10 produces a signal at an output node 17 that represents an inverted logic signal of the input applied at node 16. Note that in FIG. 1, capacitor C.sub.TOT represents the total node capacitance at node 17 of memory cell 10. In addition, arrow 18 represents a high-energy particle, such as an alpha or neutron particle. If an alpha particle 18 passes the diffusion layer of the drain of an N-type field-effect device (e.g., field-effect device 14) when output node 17 is at a high logic level, electrons generated by the alpha particle strike are collected at the same drain. Thus, the generation of electron-hole pairs by high-energy particles has a tendency to discharge various nodes throughout a logic circuit.
In the past, researchers have been primarily concerned about soft errors in memory circuits, due to their relatively small circuit size. Soft error immunity has been calculated in such circuits by using the total node charge (Q.sub.NODE) and the overall circuit area, or memory cell diffusion area. This latter parameter is related to the total capacitance at the output node of the memory cell. Generally speaking, the larger the diffusion area, the more charge that the output node can store.
Although methods such as that described above have proven satisfactory for memory array designs, they have failed to reliably predict soft error rates in other types of circuits such as latches and register files. Given that soft errors in these latter circuits have become a major source of overall chip failure rate as circuits continue to shrink, it is critical to establish a unified method to accurately predict soft error rates for all types of logic circuits.
As will be seen, the present invention provides a methodology that is useful in predicting soft error rates for a variety of circuits and/or processes. Moreover, the invention reflects the scaling impact of process technology, and also reveals principles for designing soft error robustness into logic circuits of any type.